In semiconductor technology, an integrated circuit pattern can be formed on a substrate using various processes including a photolithography process, ion implantation, deposition and etch. Damascene processes are utilized to form multilayer copper interconnections including vertical interconnection vias and horizontal interconnection metal lines. During a damascene process, trenches are formed in a dielectric material layer, copper or tungsten is filled in the trenches, then a chemical mechanical polishing (CMP) process is applied to remove excessive metal on the dielectric material layer and planarize the top surface.
As the integrated circuit (IC) fabrication moves to advanced technology nodes, the IC feature size scales down to smaller dimensions. For example, the trench dimensions get smaller and smaller. Accordingly, the gap-filling ability of those metallic materials is limited and the gap-filling quality and reliability are challenged. Further, the corresponding conductivity of the gap-filling metal is needed to be higher for desired performance of the interconnect structure. Thus, the interconnect material is a bottle neck for further improving the interconnect structure with required performance and reliability. Accordingly, a structure of interconnect structure and a method making the same are needed to address the above issues.